Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip by Pascal Meinerzhagen Adam Teman Robert Giterman Noa Edri Andreas Burg & Alexander Fish

Author:Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg & Alexander Fish
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

5.2.4 Lab Setup and Silicon Measurements

The test chips were packaged and measured using the test procedures described above. All ten packaged chips were fully operational across the complete range of supply voltages (MV DD) from 600 mV to 1.8 V. In order to study per-bit DRT, a single value was written to the entire array and the array was then put into standby for a given time period (t ret). Following this retention period, the array was read out and compared to the written data values. This procedure was repeated for several t ret values and the measured bit DRT was calculated as the first t ret that caused a read failure for each particular bit. In order to better emulate a typical operating scenario, a 5% write disturb was applied to the array. While the DRTs were measured for both all-“0” and all-“1” data levels, only all-“1” measurements are shown, since it was found to be the worst case of the two. This corresponds with Fig. 5.5, showing that data “1” degrades faster than data “0,” while also requiring a longer sensing period for the chosen read circuitry. The resulting retention map for one of the measured chips is shown in Fig. 5.7a. All measurements were taken at room temperature, which is considered a typical temperature for ULP applications that do not suffer from self-heating due to low computational complexity. DRT is shown on a log10 scale to better visualize the difference between cells, as it varies over several orders-of-magnitude. The lack of a systematic pattern shows that the difference between cells is primarily due to local process variations. The wide distribution of DRT is shown in Fig. 5.7b for all bitcells of ten measured dies (a total of 20,480 cells). The minimum and maximum DRTs were found to be 0.8 ms and 1978 ms, respectively. The large spread and lack of systematic pattern correspond with previous studies [9, 16].

Fig. 5.7(a) Retention time map of a 2 kb 3T GC array with MV DD = 900 mV. (b) DRT distribution of 20,480 3T GCs

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